The present invention relates to a pipeline-control-system data-processing apparatus and, more particularly, to a data processing apparatus for calculating addresses for a move instruction and a vector calculation instruction at high speed by using an operand address-calculating circuit in a pipeline-control-system instruction-processing unit.
A conventional pipeline-control-system data-processing apparatus has a first stage for reading out an instruction, a second stage for decoding the instruction, a third stage for calculating addresses, a fourth stage for reading out an operand, and a fifth stage for executing the instruction. These stages are performed in accordance with parallel processing. This pipeline-control-system data-processing apparatus comprises a main memory 1, an instruction processing unit 3, an arithmetic unit 5, a firmware (F/W) control section 7 for storing a microprogram, and an operand address calculating circuit 9, as shown in FIG. 1. The instruction processing unit 3 reads out an instruction from the main memory 1 and then supplies to the arithmetic unit 5 data and control information, which are required for execution of the readout instruction. When the readout instruction represents that the necessary operand for execution of the arithmetic operation is a storage operand (stored in the main memory 1), the address calculating circuit 9 performs a predetermined address calculation to issue a request to the main memory 1. In addition, the instruction processing unit 3 supplies the necessary data to the arithmetic unit 5. When the arithmetic unit 5 receives the necessary control information and data (for execution of the instruction) from the main memory 1 or the instruction processing unit 3, the arithmetic unit 5 performs the arithmetic operation in accordance with the instruction under the control of the microprogram stored in the F/W control section 7. The calculated result is stored in a predetermined register or memory, thus completing the execution of the instruction.
When a move instruction or a vector calculation instruction is processed by the data processing apparatus shown in FIG. 1, the operand address-calculating circuit 9 is interrupted during the execution of the above-mentioned instruction, since the processing contents of such instructions are complicated. As a result, the microprogram stored in the F/W control section 7 is substantially used to process the instructions in the arithmetic unit 5. It should be noted that a move instruction is performed such that a large amount of data, stored in a memory area A of the main memory 1 and located at consecutive addresses, is moved to a memory area B thereof and is located at other consecutive addresses. It should also be noted that a vector calculation instruction is performed such that a large amount of data, stored in the main memory 1 and located at equidistant address locations, is subjected to the read or the write access.
The arithmetic unit 5 must, therefore, calculate the consecutive operand addresses or the equidistant locations of operand addresses, in addition to its initial function of arithmetic calculation. As a result, the processing capacity of the arithmetic unit 5 is decreased.
In another conventional instruction processing system, the move instruction or the vector calculation instruction is performed by using an operand address-calculating circuit 9 in the instruction processing unit 3. This system is described in Japanese Patent Publication No. 57-56747. The operand address-calculating circuit 9 of this system is shown in FIG. 2. Referring to FIG. 2, an instruction read out from the main memory 1 is set in an instruction register 11. The move instruction, shown in FIG. 2, comprises an operation code OP, a general register number R, an index register number X, a base register number B and data D. An index register file (XR) 15 is addressed by the index register number X and generates readout data to a gate 23. A base register file (BR) 17 is addressed by the base register number B and generates readout data to a gate 25. A decoder 13 decodes the operation code OP and activates one of the gates 23 and 25 in accordance with its output signal. An adder (ADD) 27 adds the data D to the data gated through one of the gates 23 and 25. The operand address from an address register 29 is transferred to the main memory 1, so that the operand is read out from the main memory 1. According to this operand address-calculating circuit 9, the content specified by the operation code OP of the instruction register 11 is decoded by the decoder 13, and the output signal from the decoder 13 is used to control either the gate 23 coupled to the index register 15 or the gate 25 coupled to the base register 17, so that the data to be added by the adder 27 to the data D is controlled. Therefore, the result of the operand address calculation is produced by the address register 29 at high speed. Furthermore, the move instruction or the vector calculation instruction is decoded by the decoder to sequentially calculate the consecutive operand addresses or the equidistant locations of operand addresses under the control of the output generated from the decoder 13. According to this conventional technique, instruction decoding is repeatedly performed, thus prolonging the total processing time. The formats of the move instruction and the vector calculation instruction are extremely complex, so that hardware for decoding and controlling these instructions in the instruction processing unit increases in scale, resulting in inconvenience.